Wire Sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during the microchip encapsulation process.
3D Microchip Encapsulation includes a Wire Sweep Detail analysis that accounts not only for the effect of fluid flow on the wires but also for the effect of the wires on the fluid flow. To perform a Wire Sweep Detail analysis, the 3D model of the chip cavity must include the wire cavities, which are modeled as void regions in the 3D mesh.
| Wire Sweep Detail | Wire Sweep |
|---|---|
| Wire cavity regions are included (modeled as voids) in the 3D model of the chip cavity for Fill+Pack analysis. | Wire cavity regions are not included in the 3D model of the chip cavity for Fill+Pack analysis. |
| Accounts for the effect of wires on fluid flow in the Fill+Pack analysis. | The effect of wires on fluid flow is not considered in the Fill+Pack analysis. |
| Wires are modeled as 1D beam elements with wire properties, located within the void regions in the chip cavity mesh. | Wires are modeled as 1D beam elements with wire properties. |
For a Wire Sweep Detail analysis, model each wire cavity as a void region in the 3D model of the chip cavity. This is because no encapsulant polymer will fill the area occupied by the wire. In this way, the Fill+Pack analysis can account for the effect of the wires on the fluid flow as the encapsulant fills around the wire cavity regions.
The mesh near the wire cavities needs to be refined to get a good analysis result. Because a wire is very long compared to its diameter, to mesh around the wire cavities following typical aspect ratio guidelines requires too many elements. To use a reasonable number of elements for Wire Sweep Detail analysis, the chip cavity mesh will include high-aspect-ratio elements near the wire cavities.
Each wire should be meshed with 1D beam elements with wire properties assigned.
The wire elements should be located within the voids that represent the wire cavities in the 3D chip cavity mesh.