42 #ifndef QATOMIC_POWERPC_H
43 #define QATOMIC_POWERPC_H
49 #define Q_ATOMIC_INT_REFERENCE_COUNTING_IS_ALWAYS_NATIVE
56 #define Q_ATOMIC_INT_TEST_AND_SET_IS_ALWAYS_NATIVE
63 #define Q_ATOMIC_INT_FETCH_AND_STORE_IS_ALWAYS_NATIVE
70 #define Q_ATOMIC_INT_FETCH_AND_ADD_IS_ALWAYS_NATIVE
77 #define Q_ATOMIC_POINTER_TEST_AND_SET_IS_ALWAYS_NATIVE
86 #define Q_ATOMIC_POINTER_FETCH_AND_STORE_IS_ALWAYS_NATIVE
95 #define Q_ATOMIC_POINTER_FETCH_AND_ADD_IS_ALWAYS_NATIVE
100 template <
typename T>
104 #if defined(Q_CC_GNU)
106 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 2) \
107 || (!defined(__64BIT__) && !defined(__powerpc64__) && !defined(__ppc64__))
108 # define _Q_VALUE "0, %[_q_value]"
109 # define _Q_VALUE_MEMORY_OPERAND "+m" (_q_value)
110 # define _Q_VALUE_REGISTER_OPERAND [_q_value] "r" (&_q_value),
113 # define _Q_VALUE "%y[_q_value]"
114 # define _Q_VALUE_MEMORY_OPERAND [_q_value] "+Z" (_q_value)
115 # define _Q_VALUE_REGISTER_OPERAND
120 register int originalValue;
121 register int newValue;
122 asm volatile(
"lwarx %[originalValue]," _Q_VALUE
"\n"
123 "addi %[newValue], %[originalValue], %[one]\n"
124 "stwcx. %[newValue]," _Q_VALUE
"\n"
126 : [originalValue]
"=&b" (originalValue),
127 [newValue]
"=&r" (newValue),
128 _Q_VALUE_MEMORY_OPERAND
129 : _Q_VALUE_REGISTER_OPERAND
132 return newValue != 0;
137 register int originalValue;
138 register int newValue;
139 asm volatile(
"lwarx %[originalValue]," _Q_VALUE
"\n"
140 "addi %[newValue], %[originalValue], %[minusOne]\n"
141 "stwcx. %[newValue]," _Q_VALUE
"\n"
143 : [originalValue]
"=&b" (originalValue),
144 [newValue]
"=&r" (newValue),
145 _Q_VALUE_MEMORY_OPERAND
146 : _Q_VALUE_REGISTER_OPERAND
149 return newValue != 0;
155 asm volatile(
"lwarx %[result]," _Q_VALUE
"\n"
156 "xor. %[result], %[result], %[expectedValue]\n"
158 "stwcx. %[newValue]," _Q_VALUE
"\n"
160 : [result]
"=&r" (result),
161 _Q_VALUE_MEMORY_OPERAND
162 : _Q_VALUE_REGISTER_OPERAND
163 [expectedValue]
"r" (expectedValue),
164 [newValue]
"r" (newValue)
172 asm volatile(
"lwarx %[result]," _Q_VALUE
"\n"
173 "xor. %[result], %[result], %[expectedValue]\n"
175 "stwcx. %[newValue]," _Q_VALUE
"\n"
178 : [result]
"=&r" (result),
179 _Q_VALUE_MEMORY_OPERAND
180 : _Q_VALUE_REGISTER_OPERAND
181 [expectedValue]
"r" (expectedValue),
182 [newValue]
"r" (newValue)
190 asm volatile(
"eieio\n"
191 "lwarx %[result]," _Q_VALUE
"\n"
192 "xor. %[result], %[result], %[expectedValue]\n"
194 "stwcx. %[newValue]," _Q_VALUE
"\n"
196 : [result]
"=&r" (result),
197 _Q_VALUE_MEMORY_OPERAND
198 : _Q_VALUE_REGISTER_OPERAND
199 [expectedValue]
"r" (expectedValue),
200 [newValue]
"r" (newValue)
207 register int originalValue;
208 asm volatile(
"lwarx %[originalValue]," _Q_VALUE
"\n"
209 "stwcx. %[newValue]," _Q_VALUE
"\n"
211 : [originalValue]
"=&r" (originalValue),
212 _Q_VALUE_MEMORY_OPERAND
213 : _Q_VALUE_REGISTER_OPERAND
214 [newValue]
"r" (newValue)
216 return originalValue;
221 register int originalValue;
222 asm volatile(
"lwarx %[originalValue]," _Q_VALUE
"\n"
223 "stwcx. %[newValue]," _Q_VALUE
"\n"
226 : [originalValue]
"=&r" (originalValue),
227 _Q_VALUE_MEMORY_OPERAND
228 : _Q_VALUE_REGISTER_OPERAND
229 [newValue]
"r" (newValue)
231 return originalValue;
236 register int originalValue;
237 asm volatile(
"eieio\n"
238 "lwarx %[originalValue]," _Q_VALUE
"\n"
239 "stwcx. %[newValue]," _Q_VALUE
"\n"
241 : [originalValue]
"=&r" (originalValue),
242 _Q_VALUE_MEMORY_OPERAND
243 : _Q_VALUE_REGISTER_OPERAND
244 [newValue]
"r" (newValue)
246 return originalValue;
251 register int originalValue;
252 register int newValue;
253 asm volatile(
"lwarx %[originalValue]," _Q_VALUE
"\n"
254 "add %[newValue], %[originalValue], %[valueToAdd]\n"
255 "stwcx. %[newValue]," _Q_VALUE
"\n"
257 : [originalValue]
"=&r" (originalValue),
258 [newValue]
"=&r" (newValue),
259 _Q_VALUE_MEMORY_OPERAND
260 : _Q_VALUE_REGISTER_OPERAND
261 [valueToAdd]
"r" (valueToAdd)
263 return originalValue;
268 register int originalValue;
269 register int newValue;
270 asm volatile(
"lwarx %[originalValue]," _Q_VALUE
"\n"
271 "add %[newValue], %[originalValue], %[valueToAdd]\n"
272 "stwcx. %[newValue]," _Q_VALUE
"\n"
275 : [originalValue]
"=&r" (originalValue),
276 [newValue]
"=&r" (newValue),
277 _Q_VALUE_MEMORY_OPERAND
278 : _Q_VALUE_REGISTER_OPERAND
279 [valueToAdd]
"r" (valueToAdd)
281 return originalValue;
286 register int originalValue;
287 register int newValue;
288 asm volatile(
"eieio\n"
289 "lwarx %[originalValue]," _Q_VALUE
"\n"
290 "add %[newValue], %[originalValue], %[valueToAdd]\n"
291 "stwcx. %[newValue]," _Q_VALUE
"\n"
293 : [originalValue]
"=&r" (originalValue),
294 [newValue]
"=&r" (newValue),
295 _Q_VALUE_MEMORY_OPERAND
296 : _Q_VALUE_REGISTER_OPERAND
297 [valueToAdd]
"r" (valueToAdd)
299 return originalValue;
302 #if defined(__64BIT__) || defined(__powerpc64__) || defined(__ppc64__)
303 # define LPARX "ldarx"
304 # define STPCX "stdcx."
306 # define LPARX "lwarx"
307 # define STPCX "stwcx."
310 template <
typename T>
313 register void *result;
314 asm volatile(LPARX
" %[result]," _Q_VALUE
"\n"
315 "xor. %[result], %[result], %[expectedValue]\n"
317 STPCX
" %[newValue]," _Q_VALUE
"\n"
319 : [result]
"=&r" (result),
320 _Q_VALUE_MEMORY_OPERAND
321 : _Q_VALUE_REGISTER_OPERAND
322 [expectedValue]
"r" (expectedValue),
323 [newValue]
"r" (newValue)
328 template <
typename T>
331 register void *result;
332 asm volatile(LPARX
" %[result]," _Q_VALUE
"\n"
333 "xor. %[result], %[result], %[expectedValue]\n"
335 STPCX
" %[newValue]," _Q_VALUE
"\n"
338 : [result]
"=&r" (result),
339 _Q_VALUE_MEMORY_OPERAND
340 : _Q_VALUE_REGISTER_OPERAND
341 [expectedValue]
"r" (expectedValue),
342 [newValue]
"r" (newValue)
347 template <
typename T>
350 register void *result;
351 asm volatile(
"eieio\n"
352 LPARX
" %[result]," _Q_VALUE
"\n"
353 "xor. %[result], %[result], %[expectedValue]\n"
355 STPCX
" %[newValue]," _Q_VALUE
"\n"
357 : [result]
"=&r" (result),
358 _Q_VALUE_MEMORY_OPERAND
359 : _Q_VALUE_REGISTER_OPERAND
360 [expectedValue]
"r" (expectedValue),
361 [newValue]
"r" (newValue)
366 template <
typename T>
369 register T *originalValue;
370 asm volatile(LPARX
" %[originalValue]," _Q_VALUE
"\n"
371 STPCX
" %[newValue]," _Q_VALUE
"\n"
373 : [originalValue]
"=&r" (originalValue),
374 _Q_VALUE_MEMORY_OPERAND
375 : _Q_VALUE_REGISTER_OPERAND
376 [newValue]
"r" (newValue)
378 return originalValue;
381 template <
typename T>
384 register T *originalValue;
385 asm volatile(LPARX
" %[originalValue]," _Q_VALUE
"\n"
386 STPCX
" %[newValue]," _Q_VALUE
"\n"
389 : [originalValue]
"=&r" (originalValue),
390 _Q_VALUE_MEMORY_OPERAND
391 : _Q_VALUE_REGISTER_OPERAND
392 [newValue]
"r" (newValue)
394 return originalValue;
397 template <
typename T>
400 register T *originalValue;
401 asm volatile(
"eieio\n"
402 LPARX
" %[originalValue]," _Q_VALUE
"\n"
403 STPCX
" %[newValue]," _Q_VALUE
"\n"
405 : [originalValue]
"=&r" (originalValue),
406 _Q_VALUE_MEMORY_OPERAND
407 : _Q_VALUE_REGISTER_OPERAND
408 [newValue]
"r" (newValue)
410 return originalValue;
413 template <
typename T>
416 register T *originalValue;
417 register T *newValue;
418 asm volatile(LPARX
" %[originalValue]," _Q_VALUE
"\n"
419 "add %[newValue], %[originalValue], %[valueToAdd]\n"
420 STPCX
" %[newValue]," _Q_VALUE
"\n"
422 : [originalValue]
"=&r" (originalValue),
423 [newValue]
"=&r" (newValue),
424 _Q_VALUE_MEMORY_OPERAND
425 : _Q_VALUE_REGISTER_OPERAND
426 [valueToAdd]
"r" (valueToAdd *
sizeof(T))
428 return originalValue;
431 template <
typename T>
434 register T *originalValue;
435 register T *newValue;
436 asm volatile(LPARX
" %[originalValue]," _Q_VALUE
"\n"
437 "add %[newValue], %[originalValue], %[valueToAdd]\n"
438 STPCX
" %[newValue]," _Q_VALUE
"\n"
441 : [originalValue]
"=&r" (originalValue),
442 [newValue]
"=&r" (newValue),
443 _Q_VALUE_MEMORY_OPERAND
444 : _Q_VALUE_REGISTER_OPERAND
445 [valueToAdd]
"r" (valueToAdd *
sizeof(T))
447 return originalValue;
450 template <
typename T>
453 register T *originalValue;
454 register T *newValue;
455 asm volatile(
"eieio\n"
456 LPARX
" %[originalValue]," _Q_VALUE
"\n"
457 "add %[newValue], %[originalValue], %[valueToAdd]\n"
458 STPCX
" %[newValue]," _Q_VALUE
"\n"
460 : [originalValue]
"=&r" (originalValue),
461 [newValue]
"=&r" (newValue),
462 _Q_VALUE_MEMORY_OPERAND
463 : _Q_VALUE_REGISTER_OPERAND
464 [valueToAdd]
"r" (valueToAdd *
sizeof(T))
466 return originalValue;
472 #undef _Q_VALUE_MEMORY_OPERAND
473 #undef _Q_VALUE_REGISTER_OPERAND
556 template <
typename T>
562 template <
typename T>
568 template <
typename T>
574 template <
typename T>
580 template <
typename T>
586 template <
typename T>
592 template <
typename T>
597 template <
typename T>
603 template <
typename T>
626 template <
typename T>
629 return testAndSetAcquire(expectedValue, newValue);
632 template <
typename T>
635 return fetchAndStoreAcquire(newValue);
638 template <
typename T>
641 return fetchAndAddAcquire(valueToAdd);
648 #endif // QATOMIC_POWERPC_H
int fetchAndStoreRelaxed(int newValue)
void * q_atomic_fetch_and_add_acquire_ptr(volatile void *ptr, qptrdiff valueToAdd)
bool testAndSetRelease(int expectedValue, int newValue)
int q_atomic_fetch_and_store_release_ptr(volatile void *ptr, void *newValue)
static bool isFetchAndAddNative()
int q_atomic_fetch_and_store_release_int(volatile int *ptr, int newValue)
T * fetchAndAddAcquire(qptrdiff valueToAdd)
T * fetchAndAddOrdered(qptrdiff valueToAdd)
int q_atomic_fetch_and_store_acquire_ptr(volatile void *ptr, void *newValue)
int q_atomic_test_and_set_int(volatile int *ptr, int expectedValue, int newValue)
static bool isReferenceCountingNative()
int fetchAndAddRelaxed(int valueToAdd)
T * fetchAndStoreAcquire(T *newValue)
T * fetchAndAddRelease(qptrdiff valueToAdd)
int fetchAndAddAcquire(int valueToAdd)
static bool isReferenceCountingWaitFree()
T * fetchAndAddRelaxed(qptrdiff valueToAdd)
static bool isFetchAndAddNative()
bool testAndSetOrdered(T *expectedValue, T *newValue)
int q_atomic_set_int(volatile int *, int)
bool testAndSetAcquire(int expectedValue, int newValue)
static bool isFetchAndStoreNative()
int q_atomic_test_and_set_release_ptr(volatile void *ptr, void *expectedValue, void *newValue)
#define QT_BEGIN_NAMESPACE
static bool isTestAndSetNative()
static bool isTestAndSetNative()
static bool isFetchAndStoreNative()
T * fetchAndStoreRelaxed(T *newValue)
static bool isFetchAndAddWaitFree()
bool testAndSetRelaxed(int expectedValue, int newValue)
T * fetchAndStoreRelease(T *newValue)
bool testAndSetRelease(T *expectedValue, T *newValue)
void * q_atomic_fetch_and_add_release_ptr(volatile void *ptr, qptrdiff valueToAdd)
int q_atomic_increment(volatile int *)
static bool isFetchAndStoreWaitFree()
int q_atomic_test_and_set_ptr(volatile void *ptr, void *expectedValue, void *newValue)
static bool isTestAndSetWaitFree()
int q_atomic_test_and_set_acquire_ptr(volatile void *ptr, void *expectedValue, void *newValue)
bool testAndSetAcquire(T *expectedValue, T *newValue)
int q_atomic_test_and_set_acquire_int(volatile int *ptr, int expectedValue, int newValue)
void * q_atomic_set_ptr(volatile void *, void *)
static bool isFetchAndAddWaitFree()
T * fetchAndStoreOrdered(T *newValue)
void * q_atomic_fetch_and_add_ptr(volatile void *ptr, qptrdiff valueToAdd)
static bool isFetchAndStoreWaitFree()
int q_atomic_decrement(volatile int *)
bool testAndSetRelaxed(T *expectedValue, T *newValue)
int fetchAndStoreAcquire(int newValue)
static bool isTestAndSetWaitFree()
bool testAndSetOrdered(int expectedValue, int newValue)
int q_atomic_fetch_and_add_acquire_int(volatile int *ptr, int valueToAdd)
int q_atomic_test_and_set_release_int(volatile int *ptr, int expectedValue, int newValue)
int q_atomic_fetch_and_store_acquire_int(volatile int *ptr, int newValue)
int fetchAndAddOrdered(int valueToAdd)
int fetchAndStoreOrdered(int newValue)
int q_atomic_fetch_and_add_int(volatile int *ptr, int valueToAdd)
int q_atomic_fetch_and_add_release_int(volatile int *ptr, int valueToAdd)
int fetchAndAddRelease(int valueToAdd)
int fetchAndStoreRelease(int newValue)