Electronics Board Summary Sample

/**
 * Electronics Board Summary Sample
 * Demonstrates reading the open PCB layout: board title, placed component and copper network overview, breakdown of geometry, layer stack, design rule check results, and the linked schematic when the design includes one.
 *
 * For this sample script to run, the active Fusion document must have an electronics PCB layout as the active product.
 */

import { adsk } from '@adsk/fusion';

/** NIDL exposes this as `number`, but TypeScript codegen skips the reserved keyword. */
function ecadNumber(obj: adsk.electron.Layer | adsk.electron.Sheet): number {
  return (obj as unknown as { number: number }).number;
}

function run(): void {
  const app = adsk.core.Application.get();
  if (!app) throw new Error('No adsk.core.Application.');

  try {
    const product = app.activeProduct;
    if (!product) {
      adsk.log('No active product.');
      return;
    }
    const board = product as unknown as adsk.electron.Board;

    adsk.log('Board: ' + board.name);
    adsk.log('  headline: ' + board.headline);

    adsk.log(
      '  components: ' +
        board.elements.count +
        '  copper networks: ' +
        board.signals.count +
        '  layers: ' +
        board.layers.count,
    );

    const sigs = board.signals;
    adsk.log('  per copper network:');
    for (let i = 0; i < sigs.count; i++) {
      const sig = sigs.item(i);
      if (!sig) continue;
      const traces = sig.wires.count;
      const pours = sig.polyPours.count;
      const v = sig.vias.count;
      const contacts = sig.contactRefs.count;
      const tot = traces + pours + v + contacts;
      adsk.log('    ' + sig.name);
      adsk.log(
        '      traces=' +
          traces +
          ' pours=' +
          pours +
          ' vias=' +
          v +
          ' contacts=' +
          contacts +
          ' total=' +
          tot,
      );
    }

    const lays = board.layers;
    adsk.log('  per layer:');
    for (let i = 0; i < lays.count; i++) {
      const ly = lays.item(i);
      if (!ly) continue;
      adsk.log(
        '    [' + ecadNumber(ly) + '] ' + ly.name + ' used=' + ly.used + ' visible=' + ly.visible,
      );
    }

    adsk.log('  design rule check errors: ' + board.errors.count);

    const sch = board.linkedSchematic;
    if (sch) {
      adsk.log('  linked schematic: ' + sch.name);
    }
  } catch (err) {
    adsk.log('Failed:\n' + String(err));
  }
}

run();

#include <Core/CoreAll.h>
#include <Electron/ElectronAll.h>

#include <string>

using namespace adsk::core;
using namespace adsk::electron;

extern "C" XI_EXPORT bool run(const char* context)
{
    Ptr<Application> app = Application::get();
    if (!app)
        return false;

    Ptr<Product> product = app->activeProduct();
    if (!product)
    {
        app->log("No active product.");
        return false;
    }

    Ptr<Board> board = product->cast<Board>();
    if (!board)
    {
        app->log("Active product is not a board.");
        return false;
    }

    app->log("Board: " + board->name());
    app->log("  headline: " + board->headline());

    app->log(
        "  elements: " + std::to_string(board->elements()->count()) + "  copper networks: " +
        std::to_string(board->signals()->count()) + "  layers: " + std::to_string(board->layers()->count()));

    Ptr<Signals> sigs = board->signals();
    app->log("  per copper network:");
    for (size_t i = 0; i < sigs->count(); ++i)
    {
        Ptr<Signal> sig = sigs->item(i);
        const size_t traces = sig->wires()->count();
        const size_t pours = sig->polyPours()->count();
        const size_t v = sig->vias()->count();
        const size_t contacts = sig->contactRefs()->count();
        const size_t tot = traces + pours + v + contacts;
        app->log("    " + sig->name());
        app->log(
            "      traces=" + std::to_string(traces) + " pours=" + std::to_string(pours) +
            " vias=" + std::to_string(v) + " contacts=" + std::to_string(contacts) + " total=" + std::to_string(tot));
    }

    Ptr<Layers> lays = board->layers();
    app->log("  per layer:");
    for (size_t i = 0; i < lays->count(); ++i)
    {
        Ptr<Layer> ly = lays->item(i);
        app->log(
            "    [" + std::to_string(ly->number()) + "] " + ly->name() + " used=" +
            std::string(ly->used() ? "True" : "False") + " visible=" + std::string(ly->visible() ? "True" : "False"));
    }

    app->log("  design rule check errors: " + std::to_string(board->errors()->count()));

    Ptr<Schematic> sch = board->linkedSchematic();
    if (sch)
        app->log("  linked schematic: " + sch->name());

    return true;
}

# For this sample script to run, the active Fusion document must have an electronics PCB layout as the active product.

import adsk.core, adsk.electron, traceback


def run(context):
    app = adsk.core.Application.get()
    try:
        board = adsk.electron.Board.cast(app.activeProduct)
        if not board:
            app.log("Active product is not a board.")
            return

        app.log("Board: {}".format(board.name))
        app.log("  headline: {}".format(board.headline))

        app.log("  components: {}  copper networks: {}  layers: {}".format(
            board.elements.count, board.signals.count, board.layers.count))

        sigs = board.signals
        app.log("  per copper network:")
        for i in range(sigs.count):
            sig = sigs.item(i)
            traces = sig.wires.count
            pours = sig.polyPours.count
            v = sig.vias.count
            contacts = sig.contactRefs.count
            tot = traces + pours + v + contacts
            app.log("    {}".format(sig.name))
            app.log(
                "      traces={} pours={} vias={} contacts={} total={}".format(
                    traces, pours, v, contacts, tot))

        lays = board.layers
        app.log("  per layer:")
        for i in range(lays.count):
            ly = lays.item(i)
            app.log("    [{}] {} used={} visible={}".format(
                ly.number, ly.name, ly.used, ly.visible))

        app.log("  design rule check errors: {}".format(board.errors.count))

        sch = board.linkedSchematic
        if sch:
            app.log("  linked schematic: {}".format(sch.name))
    except Exception:
        app.log("Failed:\n{}".format(traceback.format_exc()))